1. Field of the Invention
The present invention is related to a device and method for protecting data in a semiconductor memory, and more particularly, to a security circuit for a semiconductor memory which provides excellent security and safety even with a small number of pads, and a method of protecting stored data using the same.
2. Discussion of the Related Art
In general, a semiconductor memory has a plurality of pads used as input/output terminals. One of the pads is used as a memory write enable pin. To protect data stored in the memory, a fuse is provided between the pad and the memory. The fuse is blown after data is written to the memory to prevent data from being subsequently written thereon through the pad.
A conventional security circuit for a semiconductor memory will be explained with reference to the attached drawing. FIG. 1 illustrates a conventional security circuit for a semiconductor memory.
Referring to FIG. 1, the conventional security circuit for a semiconductor memory is provided with a first pad PAD1 connected to a memory IC for use as a write enable terminal, a fuse 3 connected between the first pad PAD1 and the memory IC for isolating the inner memory IC from the first pad PAD1 after data has been written to the memory IC, a second pad PAD2 connected to the memory IC is parallel with the first pad PAD1 for applying a power after the fuse 3 is blown, an electrostatic protection part 1 having a plurality of transistors Q1-Q3 for protecting inflow of a static electricity into the inner memory IC through the second pad PAD2, and a resistor 4 for preventing floating of an isolated portion when the fuse is blown. A switching transistor Q4 is also included for switching a voltage applied to the second pad PAD2.
The operation of the conventional security circuit for a semiconductor memory will be explained hereinafter. A high level signal is applied to the first pad PAD1, which functions as a write enable terminal, for writing a data on the memory. After the data is written on the memory, when an enable signal is given to the first pad PAD1 in continuation, either the stored data is erased or other data is overwritten. Therefore, in order to prevent overwriting or erasing of data, the fuse 3 is blown by applying a high voltage to the first pad PAD1 and grounding the second pad PAD2. Once fuse 3 is blown, even if a high level signal is applied to the first pad PAD1, a memory write mode is not enabled. Furthermore, even if a high level signal is applied to the second pad PAD2, no enable signal is applied because a gate and drain of the transistor Q1 in the electrostatic protection part 1 are grounded. Thus, the data stored in an inner memory can be secured.
However, the aforementioned background art security circuit for a semiconductor memory has the following, and other, problems.
First, the security circuit is vulnerable to static electricity because no electrostatic circuit is provided to the first pad as a provision for applying a high voltage to the first pad in blowing the fuse.
Second, the conventional security circuit is difficult to incorporate into a device having a small number of pins, such as a smart card, because the conventional security circuit requires the first and second pads for blowing the fuse.
Third, the conventional security circuit has a limitation on services of the pads because signals both on the first and second pads should be the same.